Most non-volatile memory LSI's such as EPROM's or flash EEPROM's require two kinds of power supply voltages. A first power supply voltage VDD is a power supply voltage which is necessary at the time of reading, at the time of programming or at the time of other operating modes. For example, in a general EPROM, VDD is 5 V.
A second power supply voltage VPP is a power supply voltage which is necessary for programming or erasing a non-volatile memory. For example, in a general EPROM, VPP is 12 V.
It is necessary that the first power supply voltage VDD is within a rated voltage range (for example, generally 5 V.+-.10%) in a period of time when the memory LSI is in an operating condition. It is necessary that the second power supply voltage VPP is a high voltage (for example, generally 12 V.+-.5%) at the time of programming or erasure and is within a range between the ground voltage and the first power supply voltage VDD at the time of reading or stand-by.
In such a case, a power supply voltage converting circuit incorporated in the memory LSI is required to have a function and a performance which will be explained hereinbelow.
Namely, when the second power supply voltage VPP is lower than the first power supply voltage VDD, as at the time of reading or stand-by, it is necessary that a current path (or leakage current) from the first power supply voltage VDD to the second power supply voltage VPP is prevented from being generated. If such a leakage current is generated, an unnecessary current is consumed.
Also, it is necessary that an output of the power supply voltage converting circuit is clamped by the first power supply voltage VDD when the second power supply voltage VPP is lower than the first power supply voltage VDD and assumes the second power supply voltage VPP when the second power supply voltage VPP is higher than the first power supply voltage VDD by a predetermined value or more. If the output of the power supply voltage converting circuit is the same as the second power supply voltage VPP when the second power supply voltage VPP is lower than the first power supply voltage VDD, a circuit connected to the output of the power supply voltage converting circuit becomes unable to normally operate at the time of reading or stand-by since the voltage is low.
Therefore, the power supply voltage converting circuit employs a system in which the switching to either the second power supply voltage VPP or the first power supply voltage VDD is made in accordance with the value of the second power supply voltage VPP or a control signal such as a program signal.
In the prior art, however, a voltage higher than the second power supply voltage VPP is required for operation of the above-mentioned switching, as will be explained hereinbelow.
FIG. 4 shows a circuit diagram of the conventional power supply voltage converting circuit. In the figure, reference symbol VC1 denotes a power supply voltage converting circuit. At terminals T21 to T25, the power supply voltage converting circuit VC1 is connected to an external circuit and other circuits of a memory LSI.
The terminal T21 is an input terminal supplied with the second power supply voltage VPP, and reference symbol N21 denotes a signal line of VPP. The terminal T22 is an input terminal supplied with the first power supply voltage VDD, and symbol N22 denotes a signal line of VDD. The terminal T23 is an input terminal supplied with a first control input voltage VCNT, and symbol N23 denotes a signal line of VCNT. The terminal T24 is an input terminal supplied with a second control input voltage VCNTB, and symbol N27 denotes a signal line of VCNTB. The terminal T25 is an output terminal for outputting an output voltage VINT of the power supply voltage converting circuit VC1, and symbol N26 denotes a signal line of VINT.
Transistors M21 to M24 are N-channel enhancement insulated gate field effect transistors (MOSFET's). Symbol G denotes a grounded terminal, and symbols N28 and N29 denote signal lines connected to the grounded terminal G. Symbol HVSW denotes a high voltage switching circuit, and symbol PUMP denotes a booster circuit.
Next, explanation will be made of the connection of the power supply voltage converting circuit VC1.
Connected to the high voltage switching circuit HVSW are the signal line N23 for input of the first control input voltage VCNT, the signal line N21 for input of the second power supply voltage VPP, the signal line N22 for input of the first power supply voltage VDD, the signal line N28 as a grounded signal line and the signal line N24 for output of an output voltage VX.
Connected to the booster circuit PUMP are connected the signal line N23 for input of the first control input voltage VCNT, the signal line N21 for input of the second power supply voltage VPP, the signal line N22 for input of the first power supply voltage VDD, the signal line N29 as a grounded signal line and the signal line N25 for output of an output voltage VPUMP.
The gate of the transistor M21 is connected to the signal line N24, the drain thereof is connected to the signal line N22, and the source thereof is connected to the signal line N26.
The gate of the transistor M22 is connected to the signal line N27, the drain thereof is connected to the signal line N22, and the source thereof is connected to the signal line N26.
The gate of the transistor M23 is connected to the signal line N25, the drain thereof is connected to the signal line N21, and the source thereof is connected to the signal line N26.
The gate of the transistor M24 is connected to the signal line N23, the drain thereof is connected to the signal line N21, and the source thereof is connected to the signal line N26.
In the power supply voltage converting circuit VC1, the threshold voltage Vtm of the transistors M21 to M24 is, for example, 0.8 V. The first power supply voltage VDD is a fixed voltage within a range of 0 V and 7 V, and the second power supply voltage VPP changes within a range between 0 V and 12 V.
The high voltage switching circuit HVSW outputs the second power supply voltage VPP when a low level is inputted to the signal line N23 as a control input, and outputs the ground voltage 0 V when a high level is inputted to the signal line or control input N23. The booster circuit PUMP outputs the ground voltage 0 V when a low level is inputted to the signal line or control input N23, and outputs a voltage higher than the second power supply voltage VPP (for example, VPP+3 V) when a high level is inputted to the signal line or control input N23.
Next, the operation of the power supply voltage converting circuit VC1 will be explained with reference to Table 1 and FIG. 4.
TABLE 1 ______________________________________ VDD = 0-7 V VPP = 0-12 V SIGNAL VOLTAGE/ VPP = TRANSISTOR 0 V - VDD VPP = VDD - 12 V ______________________________________ VCNT 0 V 0 V VDD VCNTB VDD VDD 0 V VX VPP VPP 0 V VPUMP 0 V 0 V VPP + 3 V VINT VDD - Vtm VDD - Vtm .about. VPP VDD M21 ON ON OFF M22 ON ON OFF M23 OFF OFF ON M24 OFF OFF ON ______________________________________
Table 1 shows the values of voltages VCNT, VX, VPUMP, VINT and VCNTB of the signal lines N23 to N27 and the switched states of the transistors M21 to M24 corresponding to the value of the second power supply voltage VPP.
First, when the value of the second power supply voltage VPP is between 0 V and the first power supply voltage VDD, the first control input voltage VCNT is 0 V, the second control input voltage VCNTB is VDD and the signal line N23 is at low level. Therefore, the output voltage VX of the high voltage switching circuit HVSW takes the second power supply voltage VPP, and the output voltage VPUMP of the booster circuit PUMP takes 0 V.
Since the transistors M21 to M24 are of N-channel enhancement type, the transistors M21 and M22 assume their turned-on conditions, and the transistors M23 and M24 assume their turned-off conditions.
In this case, the output voltage VINT appearing on the signal line N26 takes VDD-Vtm since VDD&gt;VPP.
Next, when the value of the second power supply voltage VPP is between the first power supply voltage VDD and 12 V, the first control input voltage VCNT is 0 V and the second control input voltage VCNTB is the first power supply voltage VDD, the output voltage VX of the high voltage switching circuit HVSW takes the second power supply voltage VPP and the output voltage VPUMP of the booster circuit PUMP takes 0 V.
The transistors M21 and M22 assume their turned-on conditions, and the transistors M23 and M24 assume their turned-off conditions.
In this case, the output voltage VINT appearing on the signal line N26 takes the first power supply voltage VDD if VPP&gt;(VDD+Vtm).
Further, when the value of the second power supply voltage VPP is between the first power supply voltage VDD and 12 V, the first control input voltage VCNT is the first power supply voltage VDD and the second control input voltage VCNTB is 0 V, the output voltage VX of the high voltage switching circuit HVSW takes 0 V and the output voltage VPUMP of the booster circuit PUMP takes, for example, VPP+3 V due to boosting.
In this case, since the transistors M21 and M22 assume their turned-off conditions and the transistors M23 and M24 assume their turned-on conditions, the output voltage VINT appearing on the signal line N26 takes the second power supply voltage VPP under the condition that the threshold voltage Vtm of the transistor M23 with the substrate bias effect thereof taken into consideration is smaller than 3 V.
Though the conventional power supply voltage converting circuit VC1 has been explained in the foregoing, this conventional power supply voltage converting circuit VC1 involves the following inconveniences.
Namely, in order to bring the transistor M23 into a turned-on condition to supply the second power supply voltage VPP to the signal line N26 of the output voltage VINT in the case where the second power supply voltage VPP is higher than the first power supply voltage VDD, it is necessary to make the output voltage VPUMP supplied to the gate of the transistor M23 higher than the second power supply voltage VPP. Hence the booster circuit PUMP for generating such a higher output voltage VPUMP is needed.
Generally, when a high voltage is used in an integrated circuit, the withstanding voltage of a transistor or the withstanding voltage of isolation between transistors is high. Therefore, the rule of a pattern layout should be moderated as compared with a general transistor, or an excess masking step for ensuring the high withstanding voltage should be added.
As a result, the pattern layout area of the integrated circuit is increased or the increase in number of fabrication steps brings about an increase in fabrication cost. The increase in fabrication cost becomes significant as the voltage value becomes higher.
In the above-mentioned power supply voltage converting circuit VC1, too, such inconveniences are encountered since it is necessary to generate a voltage higher than the second power supply voltage VPP by the booster circuit PUMP.
Also, when the second power supply voltage VPP is lower than the first power supply voltage VDD, the highest possible voltage as the output voltage VINT by the power supply voltage converting circuit VC1 is VDD-Vtm. As a result, the output voltage VINT becomes smaller than VDD and hence there may be the case where a circuit supplied with the output voltage VINT becomes slow in operating speed or becomes inoperative.
Further, since the power supply voltage converting circuit VC1 is provided for conversion of the power supply voltage, it is preferable that the output impedance of the power supply voltage converting circuit VC1 when the output voltage VINT is outputted is made as small as possible.
However, when the second power supply voltage VPP is outputted as the output voltage VINT, the output impedance of the transistor M23 becomes considerably large. This is because an ON current of the transistor M23 is represented by a triode region of the transistor as shown by the following equation: EQU (ON current of transistor M23)=.beta..times.(Vgs-Vtm)Vds-Vds.sup.2 /2(1)
where .beta. is a constant determined by the mobility of the transistor, the thickness of a gate oxide film, and the gate length and gate width of the transistor, Vgs a difference in potential between the gate and the source of the transistor M23, and Vds, a difference in potential between the drain and the source of the transistor M23.
In the power supply voltage converting circuit VC1, the potential difference between the gate and the source is small, for example, 3 V and the threshold voltage Vtm comes to, for example, 2 V due to the substrate bias effect. Therefore, it is obvious from equation (1) that the value of Vgs-Vtm, and hence the ON current cannot be made large.
As another prior art, JP-A-5-101686 has disclosed a microcomputer having an EPROM incorporated therein and more particularly a circuit in such a microcomputer with which a leakage current from a VDD terminal supplied with a microcomputer driving voltage is prevented from flowing toward a VPP terminal supplied with a data writing voltage.
In this circuit, the leakage current from the VDD terminal to the VPP terminal can be prevented if the value of the writing voltage VPP is not larger than the driving voltage VDD subtracted by a value corresponding to the threshold voltage of a P-channel MOS transistor (for example, VPP is equal to or smaller than 4.2 V when VDD is 5 V and the absolute value of the threshold voltage of the P-channel MOS transistor is 0.8 V).
However, when the value of the writing voltage VPP is, for example, a voltage between 4.2 V and 5 V, the transistor for preventing the leakage current is not brought into a turned-on condition, and it is therefore difficult to completely arrest the leakage current from the VDD terminal to the VPP terminal.
Further, when the writing voltage VPP is higher than the driving voltage VDD and a control signal PGM takes a low level, the gate of a transistor connected between the VPP terminal and an output signal line is inputted with a voltage corresponding to the subtraction of the forward voltage of a diode from the writing voltage VPP. Therefore, the transistor is not brought into a completely turned-off condition and hence a leakage current may flow from the VPP terminal to the VDD terminal.